文档介绍：实验二、三:quartusⅡ:(a_gt,a_eq,a_lt,a,b);inputa,b;outputa_gt,a_eq,a_lt;assigna_gt=a&~b;assigna_eq=a&b|~a&~b;assigna_lt=~a&b;(codeout,indec);input[3:0]indec;output[6:0]codeout;reg[6:0]codeout;always@(indec)begincase(indec)4'd0:codeout=7'b1111110;4'd1:codeout=7'b0110000;4'd2:codeout=7'b1101101;4'd3:codeout=7'b1111001;4'd4:codeout=7'b0110011;4'd5:codeout=7'b1011011;4'd6:codeout=7'b1011111;4'd7:codeout=7'b1110000;4'd8:codeout=7'b1111111;4'd9:codeout=7'b1111011;default:codeout=7'b1001111;:::(clk,ud,q,co);inputclk,ud;outputreg[3:0]q;outputco;assignco=((q==9)&&ud)||((q==0)&&(!ud));always@(posedgeclk)begin if(ud) begin if(q>8)q<=0; elseq<=q+1'd1; end else begin if(q==0)q<=4'd9; elseq<=q-1'd1; end :脉冲宽度调制(PMW)实验实验代码modules1909(clk,h,l,out); inputclk; input[3:0]h,l; outputregout; reg[6:0]t; reg[11:0]fcnt; wire[6:0]z; regclk1; assignz=h*10+l; always@(posedgeclk) begin if(fcnt>=12'd2499) beginclk1<=~clk1;fcnt<=0;end else t<=fcnt+1;end end always@(posedgeclk1) begin if(t<z) beginout=1;end elseif(t>=7'd99) t=0;out=0;end elsebeginout=0;end t=t+1; endendmodule