数字电子技术iiiii.ppt

文档介绍：Figure 14–1 Example of VCC and ground connection and distribution in an IC package. Other pin connections are omitted for simplicity. Thomas L. FloydDigital Fundamentals, 9eCopyright ?2006 by Pearson Education, Saddle River, New Jersey 07458All rights 14–2 Input and output logic levels for CMOS. Thomas L. FloydDigital Fundamentals, 9eCopyright ?2006 by Pearson Education, Saddle River, New Jersey 07458All rights 14–3 Input and output logic levels for TTL. Thomas L. FloydDigital Fundamentals, 9eCopyright ?2006 by Pearson Education, Saddle River, New Jersey 07458All rights 14–4 Illustration of the effects of input noise on gate operation. Thomas L. FloydDigital Fundamentals, 9eCopyright ?2006 by Pearson Education, Saddle River, New Jersey 07458All rights 14–5 Illustration of noise margins. Values are for 5 V CMOS, but the principle applies to any logic family. Thomas L. FloydDigital Fundamentals, 9eCopyright ?2006 by Pearson Education, Saddle River, New Jersey 07458All rights 14–6 Currents from the dc supply. Conventional current direction is shown. Electron flow notation is opposite. Thomas L. FloydDigital Fundamentals, 9eCopyright ?2006 by Pearson Education, Saddle River, New Jersey 07458All rights 14–7 Power-versus-frequency curves for TTL and CMOS. Thomas L. FloydDigital Fundamentals, 9eCopyright ?2006 by Pearson Education, Saddle River, New Jersey 07458All rights 14–8 A basic illustration of propagation delay time. Thomas L. FloydDigital Fundamentals, 9eCopyright ?2006 by Pearson Education, Saddle River, New Jersey 07458All rights 14–9 Propagation delay times. Thomas L. FloydDigital Fundamentals, 9eCopyright ?2006 by Pearson Education, Saddle River, New Jersey 07458All rights 14–10 Loa