文档介绍：上海交通大学
硕士学位论文
深亚微米集成电路时钟线网的设计布线和优化算法研究
姓名:刘锋
申请学位级别:硕士
专业:电磁场与微波技术
指导教师:毛军发
20060101
上海交通大学硕士学位论文摘要
深亚微米集成电路时钟线网的设计布线和优化算法研究
摘要
随着工艺进入深亚微米阶段,超大规模集成电路的特征尺寸在不断缩小,同时
芯片的密度和工作频率相应在大幅度的提高。在深亚微米阶段,物理设计中互连线
造成的时延已经超过门时延,电路的性能越来越依赖于互连线线网的性能。由于时
钟信号的分布对于同步数字系统的性能至关重要,深亚微米集成电路时钟线网设计、
布线和优化对当前的EDA工具提出巨大的挑战,深入研究其布线和优化算法有着重
大的意义。
本文在回顾了深亚微米集成电路时钟线网的互连线建模、设计、布线和优化算
法已有成果的基础上,提出了一种新的互连线时延模型和一种新的同时进行布线和
线宽优化的时钟线网构造算法。新时延模型针对树形互连线,提出“等效ABCD矩阵”
的概念,在此基础上通过二阶矩匹配估算树形互连线时域响应,并通过曲线拟合给
出了解析形式的50%时延估算公式。新模型保证结果的稳定性,并且大大快于传统的
仿真方法。实验表明,新模型与电路仿真软件HSPICE仿真结果相比较误差小于15%。
基于新的精确的时延模型,本文对将更精确的模型与时钟线网线宽优化算法相
结合做了初步的探索。
最后,基于已有的时钟线网布线和优化算法,本文提出一种同时布线和线宽优
化的时钟线网构造算法,新算法相对于未进行优化的布线结果能够减少50%左右的
路径时延。

关键词:深亚微米,零偏差,时钟布线,线宽优化
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上海交通大学硕士学位论文 ABSTRACT
DESIGN, ROUTING AND OPTIMIZATION OF CLOCK
WORKS FOR DEEP SUBMICRON
INTEGRATED CIRCUIT
ABSTRACT
Due to the VLSI technology rapid progressing and the feature size continued
shrinking, the density and operation frequency of IC have been increased greatly. In the
stage of very deep submicron technology, the delay caused by interconnect in physical
design has exceeded the gate delay, works has e the dominant factor
in determining circuit performance and reliability. The distribution of clock signals is
critical to both the operation and performance of synchronous digital systems, therefore,
the research on the design, routing and optimization algorithm for clock distribution
network is more and more important.
After reviewing the achievement of work modeling, clock
work design, routing and optimization, a novel stable delay calculation
model for interconnect tree and a novel algorithm for constructing clock distribution
network by simultaneously routing and wire-sizing are proposed.
The new interconnect delay model is based on the distributed RLC parameter model.
The new model calculates the “equivalent ABCD matrix” of the interconnect tree for
approximations of transfer