文档介绍：2019/11/(CPU)结构包括三个部分:CPU内核、仿真逻辑单元和CPU信号。,并实现对设备的测试和调试功能。CPU的信号主要包括4种:①存储器接口信号②时钟和控制信号③复位和中断信号④仿真信号第2页/共33页2019/11/223F281xDSP的CPU单元结构框图第3页/共33页2019/11/224C28x的CPU主要由总线、CPU寄存器、程序地址发生器和控制逻辑、地址寄存器算术单元(ARAU)、算术逻辑单元(ALU)、乘法器和移位器等逻辑部件组成,还包括指令队列和指令译码单元、中断处理逻辑等。ALU为32位的运算逻辑单元,主要执行算术运算和布尔运算。在运算之前,ALU从寄存器、数据存储器或程序控制逻辑单元接收数据,然后进行运算,最后把结果存入寄存器或数据存储器中。32位的乘法器,可执行32×32位的补码乘法,并产生64位的结果。乘法器采用32位乘数寄存器(XT,)、32位乘积寄存器(P)和32位累加器(ACC)。CPU的移位器实现对操作数的移位操作。第4页/共33页2019/11/225FastprogramexecutionoutofbothRAMandFlashmemory100-elerationTechnology150MIPSoutofRAMfortime-criticalcodeControlPeripheralsMemorySub-SystemEventManagersUltra-Fast12-&holdsenablesimultaneoussamplingAutoSequencer,upto16conversionsw/municationsPorts150MIPSperformanceSinglecycle32x32-bitMAC(ordual16x16MAC)VeryFastInterruptResponseSinglecycleread-modified-writeF24x/patibleHigh-PerformanceCPU(C28xTMDSPCore)MemoryBus128KwFlash+2KwOTP4KwBootROM18KwRAMCodesecurityXINTF32-bitRegisterFileReal-TimeJTAG32-bitTimers(3)150MIPsC28xTM32-bitDSP32x32-bitMultiplierRMWAtomicALUInterruptManagementEventMgrAEventMgrB12--UARTASCI-UARTBSPIPeripheralBusTMS320F2812/TMS320F2810MostPowerful-MostIntegratedDualFunctionDigitalSignalController第5页/共33页2019/11/226Fast&flexibleinterruptmanagementsignificantlyreduceinterruptlatencySingle-cycle32-putationallyintensivecontrolalgorithmsmoreefficientC28xTMDSPCoreThree32-bittimerssupportmultiplecontrolloops/-modified-writeinanymemorylocationand32-bitregistersimprovecontrolalgorithmefficiencyReal-timeJTAGdebugshortensdevelopmentcycleC28xTM32-bitDSPInterruptManagement32-bitRegisterFileReal-TimeJTAG32-bitTimers(3)32x32bitMultiplierRMWAtomicALUMostC/C++Efficient32-patiblewiththeTMS320C24x™DSPfamily第6页/共33页2019/11/2272812DSP总线结构多组总线并行机制。程序读、数据读、数据写三种情况。内部地址总线,三组AddressBus:程序读地址总线PAB(ProgramAddressBus)(0:21)22根,4MW。数据读地址总线DRA