数电实验报告半加全加器.doc

文档介绍：数电实验报告半加全加器实验二半加/减器与全加/减器一、实验目的:(1)掌握全加器和半加器的逻辑功能。(2)熟悉集成加法器的使用方法。(3)了解算术运算电路的结构。二、实验设备:1、74LS00(二输入端四与非门)2、74LS86(二输入端四异或门)3、数字电路实验箱、导线若干。(74LS00引脚图)(74LS86引脚图)三、实验原理:两个二进制数相加,叫做半加,实现半加操作的电路,称为半加器。A表示被加数,B表示加数,S表示半加和,Co表示向高位的进位。全加器能进行加数、被加数和低位来的信号相加,并给出该位的进位信号以及和。四、实验内容:用74LS00和74LS86实现半加器、全加器的逻辑电路功能。(一)半加器、半减器M=0时实现半加,M=1时实现半减,真值表如下::(1)familiarwiththedrawingprocessistheunderstandingofthewholeproject,,clarifythedominantsizeoftheentirelocation,closepositionsize,rotation,closeapproach,andthearchitecturalstyle,andhaveaclearunderstandingofthewholeC功能MABS0000000110半加010100110**********半减1101011100(半加器图形符号)2、(1)S真值表:MA00011110B0011011001S,AB,AB,A,B(2)C真值表:MA00011110B0000010101C,B(A,M):(1)familiarwiththedrawingprocessistheunderstandingofthewholeproject,,clarifythedominantsizeoftheentirelocation,closepositionsize,rotation,closeapproach,andthearchitecturalstyle,andhaveaclearunderstandingofthewhole(二)全加器、全减器M=0实现全加,M=1实现全减,MABSi-1i0000000001100010100011010100100101010110010111111000001001101010101011011100101101011**********S,A,B,Ci-1C,BC,(M,A)(B,C)ii-1五、实验结果S,AB,AB,A,B半加器:C,B(A,M)S,A,B,C全加器:i-1C,CM,C