文档介绍：SYSTEMVERILOG FOR VERIFICATION
A Guide to Learning the Testbench Language Features
SYSTEMVERILOG FOR VERIFICATION
A Guide to Learning the Testbench Language Features
CHRIS SPEAR
Synopsys, Inc.
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Chris Spear
Synopsys, Inc.
377 Simarano Drive
Marlboro, MA 01752
SystemVerilog for Verification:
A Guide to Learning the Testbench Language Features
Library of Congress Control Number: 2006926262
ISBN-10: 0-387-27036-1 e-ISBN-10: 0-387-27038-8
ISBN-13: 9780387270364 e-ISBN-13: 9780387270388
Printed on acid-free paper.
¤ 2006 Springer Science+Business Media, LLC
All rights reserved. This work may not be translated or copied in whole or in part without
the written permission of the publisher (Springer Science+Business Media, LLC, 233 Spring
Street, New York, NY 10013, USA), except for brief excerpts in connection with reviews or
scholarly analysis. Use in connection with any form of information storage and retrieval,
electronic adaptation, computer software, or by similar or dissimilar methodology now
known or hereafter developed is forbidden.
The use in this publication of trade names, trademarks, service marks and similar terms,
even if they are not identified as such, is not to be taken as an expression of opinion as to
whether or not they are subject to proprietary rights.
Printed in the United States of America.
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This book is dedicated to my wonderful wife Laura,
whose patience during this project was invaluable,
and my children, Allie and Tyler, who kept me laughing.
Contents
List of Examples xi
List of Figures xxi
List of Tables xxiii
Foreword xxv
Preface xxvii
Acknowledgments xxxiii
1. VERIFICATION GUIDELINES 1
Introduction 1
The Verification Process 2
The Verification Plan 4
The Verification Methodology Manual 4
Basic Testbench Functionality 5
Directed Testing 5
Methodology Basics 7
Constrained-Random Stimulus 8
What Should You R