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Transactional Memory
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Synthesis Lectures puter Architecture
Editor
Mark D. Hill, University of Wisconsin, Madison
Synthesis Lectures puter Architecture publishes 50- to 150 page publications on topics
pertaining to the science and art of designing, analyzing, selecting and interconnecting hardware
components to puters that meet functional, performance and cost goals.
Transactional Memory
James R. Larus and Ravi Rajwar
2007
puting puter Architects
Tzvetan S. Metodi, Frederic T. Chong
2006
Copyright © 2007 by Morgan & Claypool
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or
transmitted in any form or by any means—electronic, mechanical, photocopy, recording, or any
other except for brief quotations in printed reviews, without the prior permission of the publisher.
Transactional Memory
James R. Larus and Ravi Rajwar
ISBN-10: 1598291246 paperback
ISBN-13: 9781598291247 paperback
ISBN-10: 1598291254 ebook
ISBN-13: 9781598291254 ebook
DOI
A lecture in the Morgan & Claypool Synthesis Series
SYNTHESIS LECTURES PUTER ARCHITECTURE #2
Lecture #2
Series Editor: Mark D. Hill, University of Wisconsin, Madison
Series ISSN: 1935-3235 print
Series ISSN: 1935-3243 electronic
First Edition
10 9 8 7 6 5 4 3 2 1
Printed in the United States of America
P1: IML/FFX P2: IML/FFX QC: IML/FFX T1: IML
MOBK061-FM MOBK061- January 3, 2007 15:13
Transactional Memory
James R. Larus
Microsoft
larus@
Ravi Rajwar
Intel Corporation
@
SYNTHESIS LECTURES PUTER ARCHITECTURE #2
M
&C Morgan & Claypool Publishers
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