文档介绍：SYSTEMVERILOG FOR VERIFICATION
A Guide to Learning the Testbench Language Features
CHRIS SPEAR
Synopsys, Inc.
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Contents
List of Examples xi
List of Figures xxi
List of Tables xxiii
Foreword xxv
Preface xxvii
Acknowledgments xxxiii
1. VERIFICATION GUIDELINES 1
Introduction 1
The Verification Process 2
The Verification Plan 4
The Verification Methodology Manual 4
Basic Testbench Functionality 5
Directed Testing 5
Methodology Basics 7
Constrained-Random Stimulus 8
What Should You Randomize? 10
Functional Coverage 13
ponents 15
Layered Testbench 16
Building a Layered Testbench 22
Simulation Environment Phases 23
Maximum Code Reuse 24
Testbench Performance 24
Conclusion 25
2. DATA TYPES 27
Introduction 27
Built-in Data Types 27
viii SystemVerilog for Verification
Fixed-Size Arrays 29
Dynamic Arrays 34
Queues 36
Associative Arrays 37
Linked Lists 39
Array Methods 40
Choosing a Storage Type 42
Creating New Types with typedef 45
Creating User-Defined Structures 46
Enumerated Types 47
Constants 51
Strings 51
Expression Width 52
2. Types 53
Conclusion 53
3. PROCEDURAL STATEMENTS AND ROUTINES 55
Introduction 55
Procedural Statements 55
Tasks, Functions, and Void Functions 56
Task and Function Overview 57
Routine Arguments 57
Returning from a Routine 62
Local Data Storage 62
Time Values 64
Conclusion 65
4. BASIC OOP 67
Introduction 67
Think of Nouns, not Verbs 67
Your First Class 68
Where to Define a Class 69
OOP Terminology 69
Creating New Objects 70
Object Deallocation 74
Using Objects 76
Static Variables vs. Global Variables 76
Class Routines 78
Defining Routines Outside of the Class 79
Scoping Rules 81
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