文档介绍：湖南大学
硕士学位论文
基于CMOS工艺的锁相环频率合成器设计
姓名:龙晖
申请学位级别:硕士
专业:微电子学与固体电子学
指导教师:胡锦
20070525
硕士学位论文
摘要
锁相环(Phase-Locked Loop, PLL)电路作为时钟倍频器,以其低廉的成本和
优越的性能,成为当代微处理器必不可少的核心组成部件。锁相环位于微处理器
时钟树的最上端,其性能的优劣直接影响并决定了全芯片的最高工作频率和稳定
性。随着时钟频率的不断提高,微处理器的性能受锁相环的影响越来越大,锁相
环技术己经成为当代微处理器的核心技术之一。
本论文首先描述并分析了电荷泵锁相环频率合成器的体系结构、组成单元、
各单元的数学模型,讨论并分析了电荷泵锁相环的线性、非线性特性和噪声特性,
并给出了电荷泵锁相环器件参数的计算表达式。然后设计了一个工作在
10MHz-80MHz 的电荷泵锁相环频率合成器。设计中环形振荡器采用了具有自校
正功能的延迟单元,特别是采用了全差分结构,大大抑制了电源和衬底噪声的干
扰,稳定性有很大的提高。鉴频鉴相器增加了延迟反馈回路,减小了死区的范围。
其中的各设计均使用 Star-Hspice、Hsim 和 Cadence 设计软件,采用 CSMC µm
CMOS 工艺,完成了电路的设计、仿真、版图设计、后仿真及芯片测试。
仿真结果表明,本设计可以很好的在 2MHz-100MHz 范围内输出正确的方波
信号,锁定时间小于 10µs,频率切换过程中没有出现失锁现象。华润上华的流片
测试结果表明在-55~125℃的温度范围内,频率合成器均能稳定工作,符合军用标
准,完全可以在军用数字信号处理器中用做时钟发生器。

关键词:CMOS;锁相环;频率合成器;电荷泵
I
基于 CMOS 工艺的锁相环频率合成器设计
Abstract
Attribute to the low cost and good performance, Phase-Locked Loop (PLL)
which works as a clock synthesizer, has e a necessary and core part in modem
microprocessors. It works on the top of the clock tree. Its performance directly
influences and decides the highest frequency and stability of the whole chip. The
higher the clock frequency is, the more PLL influences the performance of
microprocessors. PLL technique has been one of the core techniques in modern
microprocessor design.
In this paper we described and analyzed the architecture, as well as the block and
the mathematical model of charge pump phase locked loop (CPPLL), and then
analyzed the linear, nonlinear character and noise character of CPPLL and gave the
form for calculating the parameter of CPPLL. Next a CPPLL frequency synthesizer
was designed whose working range is 10MHz-80MHz. In order to reduce the
influence of noise from supply and substrate, full differential architecture and
self-adjusted delay cell is used to keep the output of VCO pure. Stability is good as
well. To reduce the dead-zone, a delay unit was added to feedback loop. The designs
in this paper are