文档介绍：A RISC Design:
Synthesis of the MIPS
Processor Core
A full die photograph of the MIPS R2000 RISC Microprocessor is shown above. The
1986 MIPS R2000 with five pipeline stages and 450,000 transistors was the world's first
commercial RISC microprocessor. Photograph 01995-2004 courtesy of Michael
Davidson, Florida State University, http:llr,iicro..~chipshots.
256 Rapid Prototyping of Digital Systems Chapter 14
14 A RISC Design: Synthesis of the MlPS Processor Core
The MlPS lnstruction Set and Processor
The MIPS is an example of a modem reduced instruction puter (RISC)
developed in the 1980s. The MIPS instruction set is used by NEC, Nintendo,
Motorola, Sony, and licensed for use by numerous other semiconductor
manufacturers. It has fixed-length 32-bit instructions and thirty-two 32-bit
general-purpose registers. Register 0 always contains the value 0. A memory
word is 32 bits wide.
As seen in Table , the MIPS has only three instruction formats. Only I-
format LOAD and STORE instructions reference memory operands. R-format
instructions such as ADD, AND, and OR perform operations only on data in the
registers. They require two register operands, Rs and Rt. The result of the
operation is stored in a third register, Rd. R-format shift and function fields are
used as an extended opcode field. J-format instructions include the jump
instructions.
Table MlPS 32-bit lnstruction Formats.
Field Size 6-bits 5-bits 5-bits 5-bits 5-bits 6-bits
R- Format Opcode Rs Rt Rd Shift Function
I - Format Opcode Rs Rt Addresslimmediate value
J - Format Opcode Branch target address
LW is the mnemonic for the Load Word instruction and SW is the mnemonic
for Store Word. The following MIPS assembly language putes
A=B+C.
LW $2, B ;Register 2 = value of memory at address B
LW $3, C ;Register 3 = value of memory at address C
ADD $4, $2, $3 ;Register 4 = B + C
SW $4, A ;Value of memory at a