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MOBK046-FM MOBK046- October 14, 2006 13:16
Introduction to Logic Synthesis
using Verilog HDL
i
Copyright © 2006 by Morgan & Claypool
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means—electronic, mechanical, photocopy, recording, or any other except for brief quotations
in printed reviews, without the prior permission of the publisher.
Introduction to Logic Synthesis using Verilog HDL
Robert B. Reese and Mitchell A. Thornton
ISBN-10: 1598291068 paperback
ISBN-13: 9781598291063 paperback
ISBN-10: 1598291076 ebook
ISBN-13: 9781598291070 ebook
A Publication in the Morgan & Claypool Publishers’ series
SYNTHESIS LECTURES ON DIGITAL CIRCUITS AND SYSTEMS #6
Lecture #6
Series Editor and Affliation: Mitchell A. Thornton, Southern Methodist University
Series ISSN: 1930-3166 print
Series ISSN: 1930-3174 electronic
First Edition
10 9 8 7 6 5 4 3 2 1
Printed in the United States of America
P1: JYS
MOBK046-FM MOBK046- October 14, 2006 13:16
Introduction to Logic Synthesis
using Verilog HDL
Robert B. Reese
Mississippi State University
Mitchell A. Thornton
Southern Methodist University
SYNTHESIS LECTURES ON DIGITAL CIRCUITS AND SYSTEMS #6
M
&C Morgan & Claypool Publishers
iii
iv
ABSTRACT
Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descrip-
tions of digital systems that can be synthesized into digital lists with desirable charac-
teristics. The book contains numerous Verilog examples that begin with -
works and progress to synchronous sequential logic systems. Common pitfalls in the development
of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The tar-
get audience is any one with a basic understanding of digital logic principles who wishes to learn
how to model