文档介绍：Advanced Techniques in Logic Synthesis,
Optimizations and Applications
Sunil P. Khatri · Kanupriya Gulati
Editors
Advanced Techniques
in Logic Synthesis,
Optimizations
and Applications
123
Editors
Sunil P. Khatri Kanupriya Gulati
Department of ECE Intel Corporation
333F WERC, MS 3259 2501 NW 229th Ave
Texas A&M University Hillsboro, OR 97124,
College Station, TX 77843-3259, USA
USA @
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ISBN 978-1-4419-7517-1 e-ISBN 978-1-4419-7518-8
DOI -1-4419-7518-8
Springer New York Dordrecht Heidelberg London
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Preface
The last few decades have seen a stupendous growth in the speed plex-
ity of VLSI integrated circuits. This growth has been enabled by a powerful set
of electronic design automation (EDA) tools. The earliest EDA tools were two-
level logic minimization and PLA folding tools. Subsequently, EDA tools were
developed to address other aspects of the VLSI design flow (in addition to logic
optimization) such as technology mapping, layout optimization, formal verification.
However, research in logic synthesis and optimization continued to progress rapidly