文档介绍：Verilog HDL
A guide to Digital Design
and Synthesis
Samir Palnitkar
SunSoft Press
1996
PART 1 BASIC VERILOG TOPICS 1
1 Overview of Digital Design with Verilog HDL 3
2 Hierarchical Modeling Concepts 11
3 Basic Concepts 27
4 Modules and Ports 47
5 Gate-Level Modeling 61
6 Dataflow Modeling 85
7 Behavioral Modeling 115
8 Tasks and Functions 157
9 Useful Modeling Techniques 169
PART 2 Advance Verilog Topics 191
10 Timing and Delays 193
11 Switch-Level Modeling 213
12 User-Defined Primitives 229
13 Programming Language Interface 249
14 Logic Synthesis with Verilog HDL 275
PART3 APPENDICES 319
A Strength Modeling and Definitions 321
B List of PLI Rountines 327
C List of Keywords, System Tasks, piler Directives 343
D Formal Syntax Definition 345
E Verilog Tidbits 363
F Verilog Examples 367
Part 1 Basic Verilog Topics
Overview of Digital Design with Verilog HDL
Evolution of CAD, emergence of HDLs, typical HDL-based design flow, why
[j Verilog HDL?, trends in HDLs.
Hierarchical Modeling Concepts
Top-down and bottom-up design methodology, differences between
modules and module instances, parts of a simulation, design block, stimulus
LJ block.
Basic Concepts
LJ Lexical conventions, data types, system tasks, compiler directives.
Modules and Ports
Module definition, port declaration, connecting ports, hierarchical name
[j referencing.
Gate-Level Modeling
Modeling using basic Verilog gate primitives, description of and/or and
[j buf/not type gates, rise, fall and tum-off delays, min, max, and typical
delays.
Dataflow Modeling
Continuous assignments, delay specification, expressions, operators,
[j operands, operator types.
Behavioral Modeling
Structured procedures, initial and always, blocking and nonblocking
[j statements, delay control, event control, conditional statements, multiway
branching, loops, sequential and parallel blocks.
Tasks and Func