文档介绍：IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 9, SEPTEMBER 2004 1665
Analysis of Charge-Pump Phase-Locked Loops
Pavan Kumar Hanumolu, Student Member, IEEE, Merrick Brownlee, Student Member, IEEE,
Kartikeya Mayaram, Senior Member, IEEE, and Un-Ku Moon, Senior Member, IEEE
Abstract—In this paper, we present an exact analysis for third-
order charge-pump phase-locked loops using state equations. Both
the large-signal lock acquisition process and the small-signal linear
tracking behavior are described using this analysis. The nonlinear
state equations are linearized for the small-signal condition and
the -domain noise transfer functions are derived. parison to
some of the existing analysis methods such as the impulse-invariant
transformation and -domain analysis is provided. The effect of
the loop parameters and the reference frequency on the loop phase
margin and stability is analyzed. The analysis is verified using be-
havioral simulations in MATLAB and SPECTRE.
Index Terms—Impulse invariance, jitter, loop delay., phase-
Fig. 1. Third-order CPLL block diagram.
locked loop (PLL), phase noise, state space, z-domain.
voltage controlled oscillator (VCO). The CPLL system is shown
I. INTRODUCTION
in Fig. 1. A divider is used in feedback, in applications requiring
HARGE-PUMP based phase-locked loops (CPLL) are clock multiplicatio