文档介绍：Analysis and Design of
Phase-Locked Loops
Prof. Shen-Iuan Liu
Depart. of Electrical Engineering
National Taiwan University
Taipei, Taiwan 10617, .
Tel.: (02)23635251 ext. 239
Fax: (02)23671909
Email: .
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Block diagram of a phase-locked loop
Phase detector Loop filter VCO
1 fr φ
R LPF fout
Crystal Reference
reference divider fp
1
N
Main divider
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Linear model of a phase-locked loop
θi +
I Ko
Kd= 2π F(s)
s θ
- o
1
N
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Loop Filter (2nd Order)
V 1 1 sC2R2 + 1
= F(s)=(R2 + ) ! =
I sC2 sC1 s(sC1C2R2 + C1 + C2)
I V sT + 1
F(s)= 1 2
C1 + C2 s(sT1 + 1)
R2
C1
C1C2
where T1 = R2 , T2 = R2C2
C2 C1 + C2
−1 −1 C2
!Z = T2 ,!p = T1 = !Z(1 + )
C1
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Opened-Loop Response
F (s )
! Z ! P
G(s)
! C
( )
" ! "P
K K F(s)
Opened − loop gain G(s)= d o
sN
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Opened-Loop Response
−( + )
KdKo 1 j!T2 T1
−( ) = =
Gain : G s |s j! 2 "
! C1N(1 + j!T1) T2
−1 −1 o
Phase : "(!)=tan (!T2)−tan (!T1)+180
d"(!)
Let = oat! = !
d! C
1
!C =
T1T2
Maximum Phase Margin
−1 −1
"P = tan (!CT2)−tan (!CT1)
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Opened-Loop Response
1 + j T
= ( ) = = Kd KoT 1 ! C 2
! ! C ! |G j! c | 1 ! C 1 2 " +
! CNT2 1 j! C T1
sec − tan
= " P " p = 1
T1 ! C and T2 2
! CT 1
Hence, if ωc and φp are specified,
T K K 1 +(! T )2
C = 1 " d o " C 2
1 T 2 1 +(! T )2
2 !CN C 1
T2
C2 = C1 " ( − 1)
T1
T2
R2 =
C2
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Closed-Loop Response
K K F(s)
Opened − loop gain G(s)= d o
sN
NG(s)
Closed − loop gain H(s)=
1 + G(s)
+ =
= = ω
+
+
ω
+ω
⇒ = =
+
ω
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Closed-Loop Response
ω ω
= = ω ⇒ = ω
= ω !
ω
+