文档介绍：Digital Phase Locked Loop
Design and Layout
Dali Wang
Fan Yang
12/21/2001
Contents
1. Intoduction 1
Project Overview 1
Objective Of The Project 2
Table Listing Of Specifications 2
The Design Specifications 3
The Test Specification 3
Table Of Macros 4
Table Of PinOuts 5
Known Limitations Of Current Design 5
2. Circuit Design 5
Description 5
Phase And Frequency Detector 5
Loop Filter 6
Voltage Controlled Oscillator 6
Discussion Of Tradeoffs 7
Description Of Schematics 7
Phase And Frequency Detector Schematics 7
Loop Filter Schematics 8
Voltage Controlled Oscillator Schematics 8
3. Circuit Performance 9
Schematics Simulation Results 9
Results For Some ponents (Other Than Macros) 9
Results For Large Macros 11
Entire Circuit 19
Discussion Of Results 23
4. Physical Design 25
Description ponents 25
Layout Considerations 25
Description Of Physical Layout 25
Phase And Frequency Detector 25
Loop Filter 26
Voltage Controlled Oscillator 29
Buffer 29
Floorplanning Issues 30
5. Verification 31
DRC And LVS Verification 31
Simulation Of Extracted View 33
6. Experimental Results 37
7. Summary and Conclusion 37
Between Simulation And Experimental Results 37
Suggestions For Improved Performance 37
Suggestions For Improved Design 37
Acknowledgements 37
Appendix A Schematics 38
Appendix B Physical Layout 44
Appendix C PinOut Diagram 54
1 Introduction
Project overview
Our Project in ECE547--VLSI Design and Layout is to design a high-frequency digital phase-
locked loop (PLL). We propose to implement two different frequencies: one is 20 MHz,
another one is 25 MHz.
Usually, a PLL circuit is used to synchronize an output signal, which is usually generated by
an oscillator, with a reference or input signal in frequ