文档介绍：IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 8, AUGUST 1999 1063
An All-Digital Phase-Locked Loop
(ADPLL)-Based Clock Recovery Circuit
Terng-Yin Hsu, Bai-Jue Shieh, and Chen-Yi Lee
Abstract— A new algorithm for all-digital phase-locked loops design is an important issue in digital VLSI. A problem of
(ADPLL) with fast acquisition and large pulling range is pre- portable ADPLL’s is the source of on-chip high-speed clocks.
sented in this paper. Based on the proposed algorithm, portable Theoretically, this high-speed clock should be fast enough and
cell-based implementations for clock recovery with functions of a
frequency synthesizer and on-chip clock generator pleted act as a reference clock. When ADPLL’s operate in high-
by standard cell. These modules have been designed and verified data-rate environments, a number of issues must be taken into
on a -""" m CMOS process. Test results are summarized as account, such as power dissipation, logic propagation delay,
follows: 1) the proposed ADPLL can satisfy full locked band- process variation, and so on. Hence the characteristics of on-
width and fast acquisition within one data transition; 2) the chip high-speed clocks must be limited for a target process and
on-chip clock generator can generate any target clock rate fff lok ;
and 3) the function of nonreturn-to-zero clock recovery has a flexible enough to meet design requirements. It means that an
maximum fff lok /4 recovering capability with a locking range of on-chip high-speed clock must be controllable to operate at a
(((( input ((( input /2), where ((( input is the input period. special rate.
Index Terms— All-digital phase-locked loop (ADPLL), clock Many PLL/DPLL-based designs have been developed. In
recovery, frequency synthesizer, phase-locked loop. [2], a nonreturn-to-zero (NRZ) timing recovery with a digital
phase detector (PD), analog loop filter (LF), and voltage-
controlled oscillator (VCO) are introduced for band-lim