文档介绍：Advanced Xilinx FPGA
Design with ISE
Course Agenda
© 2002 Xilinx, Inc. All Rights Reserved
Agenda
Section 1 : Optimize Your Design for Xilinx Architecture
– Core Generator System
• Lab : Core Generator System Flow
Section 2 : Achieving Timing Closure
– Timing Closure with Timing Analyzer
– Global Timing Constraints
• Lab : Global Timing Constraints
– Advance Timing Constraints
• Lab : Achieving Timing Closure with Advance Constraints
Section 3 : Improve Your Timing
– Floorplanner
• Lab: Floorplanner
Section 4 : Reduce Implementaion Time
– Incremental Design Techniques
• Lab : IDT Flow
– Modular Design Techniques
• Lab : MDT Flow
Agenda - 3 © 2002 Xilinx, Inc. All Rights Reserved
Agenda
Section 5 : Reduce Debug Time
– FPGA Editor: Viewing and Editing a Routed Design
• Lab: FPGA Editor
Section 6 : On-Chip Verification and Debugging
– ChipScope Pro
• Demo
Section 7 : Course Summary
Optional Topics
– Power Estimation with Xpower
– Advance Implementation Options
– Embedded Solutions with Power PC/MicroBlaze and Embedded Development Kit (EDK)
– Xtreme DSP Solutions with System Generator
Agenda - 4 © 2002 Xilinx, Inc. All Rights Reserved
Objectives
pleting this course, you will be able to:
• Describe Virtex™-II advanced architectural features and how they can be used to
improve performance
• Create and integrate cores into your design flow using the CORE Generator™ System
• Describe the different ISE options available and how they can be used to improve
performance
• Describe a flow for obtaining timing closure with Advance Timing Constraints
• Use FloorPlanner to improve timing
• Reduce implementation time with Incremental Design Techniques and Modular Design
Techniques
• Reduce debugging time with FPGA Editor
• On-Chip Verification with ChipScope Pro
Agenda - 5 © 2002 Xilinx, Inc. All Rights Reserved
Prerequisites
Basic knowledge of :
• Virtex™-II architecture features