文档介绍：FPGA Implementation of FIR Filter with smallest
Processor
Chao-Huang Wei, Hsiang-Chieh Hsiao, Su-Wei Tsai
Department of Electrical Engineering
Southern Taiwan University of Technology
No. 1, Nan-Tai St., Yung-Kang/Tainan, Taiwan 710, .
E-Mail:******@
Abstract - Finite impulse response (FIR) filter is the key functional "addition" and "iteration" are required for the filter processing.
block in the field of digital signal processing. A number of The "delay" operation can be done with "loading" and
implementations can be found in the public literatures, either by "storing"; the "multiplication" is inefficient with software
software or hardware solutions. The proposed design is trying to processing and hardware resource consuming; therefore it will
answer the question on whether a solution can be achieved with
be placed outside the CPU architecture. Thus, only four type
minimal cost of hardware and software, and how is its
performance. In the VLSI implementation, the hardware operations remain for the CPU to process.
complexity of the FIR filter is directly proportional to the tap shows the system architecture for a 4-tap FIR filter,
length and the bit-width of input signal. To reduce the hardware which consists of an eight bit CPU, 32 bytes program ROM, 5
cost, this can be solved with iteration calculat