文档介绍：theAndrakaCG onsulting roup
16 Arcadia Drive North Kingstown, RI 02852-1666 USA
Building a High
Performance Bit Serial
Processor in an FPGA
Raymond J. Andraka
Andraka Consulting Group
16 Arcadia Drive
North Kingstown, RI 02852-1666 USA
1996
On-Chip System
Design Conference
Andraka Consulting Group 1995
theAndrakaCG onsulting roup
16 Arcadia Drive North Kingstown, RI 02852-1666 USA
Authors/Speakers
Abstract Raymond J. Andraka
This paper describes the Current Activities Author Background
advantages and pitfalls of a bit
serial architecture by studying Ray Andraka is the chairman Ray Andraka has an MSEE
the design of a vector of the Andraka Consulting from University of
magnitude processor inside a Group, a digital hardware Massachusetts at Lowell and a
radar signal processor. The design firm specializing in BSEE from Lehigh University.
bines bit serial high performance FPGA He has originated and
arithmetic with a CORDIC designs. His current improved dozens of designs in
algorithm to process 8 million consulting activities include Xilinx, AMD, Altera, Actel,
12 bit vectors per second supporting reconfigurable Atmel, QuickLogic, and NSC
inside a single FPGA. The puter research, applying FPGAs over the past 8 years.
serial architecture has the FPGAs to next generation Many of these designs were
advantage of a pact general aviation avionics, and for high performance signal
design solution that avoids developing the electronics processing applications. His
many of the place and route package for a new medical signal processing experience
monly associated device. Ray is also writing includes over 5 years
with FPGAs. The bit clock application notes describing designing pipelined radar
required to obtain the design techniques for FPGAs. signal processors for Raytheon
required data rate pushes the and 3 years of signal detection
upper limits of today’s FPGAs. and reconstruction algorithm
Therefore, this paper also development for the U