文档介绍：A Low-Power Systolic Array-Based Adaptive Viterbi Decoder
and its FPGA Implementation
Man Guo, M. Omair Ahmad, Fellow, IEEE, . Swamy, Fellow, IEEE, and Chunyan Wang
Department of Electrical puter Engineering
Concordia University
Montreal, Quebec, Canada H3G 1M8
ABSTRACT speed over the serial and parallel architectures due to its
high degree of pipelining and multiprocessing. It can also
In this paper, the design and FPGA implementation of a
provide, for different convolutional code structures, a gen-
low-power adaptive Viterbi decoder with a constraint length
eral method for a simple adjacent cell interconnection.
of 9 and code rate of l/Z is presented. In this design, a novel
However, to design the Viterbi decoder with a large value of
systolic array-based architecture with time multiplexing and
K, say, K=9, and a code rate of r=1/2, plexity of the
arithmetic pipelining for implementing the adaptive Viterbi
computations will make the adoption of the systolic array
algorithm is used. A scheme for providing a tolerance to
architecture in 171 not feasible. In order to reduce the
clock-to-data skew to avoid timing violation is proposed. A
amount of addition. comparison, and selection (ACS) com-
process of eliminating the spurious toggles for reducing
putations, an adaptive Viterbi algorithm that is based on