文档介绍：组合逻辑电路 Chapter6 Chapter6 Combinational Logic Combinational Logic Design Practices Design Practices Chapter Outline ? Documentation Standards ? Digital Circuit Timing and Propagation delay ? Combinational Logic Design Structures : - Decoders - Encoders - Three-State Buffers - Multiplexers - EXCLUSIVE OR Gates and Parity Circuits - Comparators - Adders/ Subtractors - Arithmetic Logic Units ( ALUs ) Documentation Standard (文档标准) ? Documentation of a digital system should provide the necessary information for building, testing ,operating , and maintaining the system. ? Specification: Description of Interface and Function (说明书:接口及功能描述) ? Block Diagram: System ’ s Major Function Module and their Basic Interconnections (方框图:主要功能模块及其互联 P345 图 6-1 ) ? Schematic Diagram: showing all ponents, their types, and all interconnections (原理图( P360 图 6-17 )) Block Diagram Schematic Diagram Hierarchichal schematic structure Documentation Standard (文档标准) ? Timing Diagram: showing the logic signals as a function of time (定时图( P363 图 6-19 )) ? Structure Logic Device Description: showing the operation of the structures (结构化逻辑器件描述) ? Circuit Description : Explains how the circuit works internally. (电路描述:解释电路内部如何工作) “ Hierarchical Design ” Gate Symbols ( 门的符号) &≥11 an equivalent symbols (等效门符号(摩根定理) ) Inverter ( 反相器) Buffer ( 缓冲器) Which symbol to use? - depends on signal names and active levels. Signal Names and Active Levels (信号名和有效电平) ? Signal name : a descriptive alphanumeric label for each input/output signal. ? In real system, well-chosen names convey information to readers ? Each signal name should have an active-level associated with it. (有效电平) ? Active High (高电平有效) ? Active Low (低电平有效)