文档介绍：一: 本实验设计的是一个 8 为二进制加法计算器, 其功能就是对两个八位的二进制数执行加法运算,并可以异步清零。二:电路可划分为三部分:半加器、全加器和复位电路。 1、半加器: 真值表 ab so co 0000 0110 1010 1101 电路图 2 全加器:由半加器和或门组成电路图 3 复位电路: 复位电路通过 en 控制,当 en为‘1’时,执行加法运算,输出正确的值,当 en为‘0’时,输输出及结果为全 0. 三:实验波形仿真和 VHDL 1、仿真图: 2、 VHDL 代码 1) 半加器 h_adder : library ieee; use ; entity h_adder is port (a,b :in std_logic; co,so :out std_logic); end entity h_adder; architecture fh1 of h_adder is begin so <= not(a xor (not b));co <= a and b; end architecture fh1; 2) 或门 or2a : library ieee; use ; entity or2a is port (a,b :in std_logic; c: out std_logic); end entity or2a; architecture one of or2a is begin c <= a orb; end architecture one; 3) 全加器 f_adder : library ieee; use ; entity f_adder is port (ain,bin,cin:in std_logic; cout,sum:out std_logic); end entity f_adder; architecture fd1 of f_adder ponent h_adder port (a,b :in std_logic; co,so :out std_logic); ponent; component or2a port (a,b :in std_logic; c: out std_logic); ponent; signal d,e,f: std_logic; begin u1:h_adder port map(a=>ain,b=>bin,co=>d,so=>e); u2:h_adder port map(a=>e,b=>cin,co=>f,so=>sum); u3: or2a port map(a=>d,b=>f,c=>cout); end architecture fd1; 4) 与门 and2a : library ieee; use ; entity and2a is port (a,b :in std_logic; c: out std_logic); end entity and2a; architecture one of and2a is begin c <= a and b; end architecture o