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数字系统设计-同步数字系统.ppt

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数字系统设计-同步数字系统.ppt

上传人:lxydx 2017/12/13 文件大小:1.84 MB

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数字系统设计-同步数字系统.ppt

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文档介绍:数字系统设计 Digital System Design
2
2015 ZDMC – Lec. #1
设计准则(Design Metrics)
如何评价数字电路的性能(Figure of Merit)
成本Cost
可靠性Reliability
可扩展性Scalability
速度Speed (delay, operating frequency)
功耗Power dissipation
能耗Energy to perform a function
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2015 ZDMC – Lec. #1
同步数字系统(Digital Systems)
同步数字硬件系统Synchronous Digital Hardware Systems
Example digital representation: acoustic waveform
A series of numbers is used to represent the waveform, rather than a voltage or current, as in analog systems.
同步(Synchronous): “Clocked”- all changes in the system are controlled by a global clock and happen at the same time (not asynchronous)
数字(Digital): All inputs/outputs and internal values (signals) take on discrete values (not analog).
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2015 ZDMC – Lec. #1
数字系统例子-1
数字计算机
最大化能效
- 最小化成本
计算器
5
2015 ZDMC – Lec. #1
数字系统例子-2
数字手表
可穿戴设备
最小化功耗.
电池可维持数年
数字系统设计例子-3
The TROJAN PROOF CHIP
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2015 ZDMC – Lec. #1
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2015 ZDMC – Lec. #1
设计折中
设计规范-
功能性描述.
性能(速度)
成本(复杂性)
功耗(能量消耗)
作为设计人员必须在约束条件下实现预期的功能。
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2015 ZDMC – Lec. #1
设计表达
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2015 ZDMC – Lec. #1
Analog
Baseband
Digital Baseband
(DSP + MCU)
Power
Management
Small
Signal RF
Power
RF
Cell Phone
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2015 ZDMC – Lec. #1
Blue Gene/Q Compute chip
360 mm² Cu-45 technology (SOI)
~ B transistors
16 user + 1 service processors
plus 1 redundant processor
all processors are symmetric
each 4-way multi-threaded
64 bits PowerISA™
GHz
L1 I/D cache = 16kB/16kB
L1 prefetch engines
each processor has Quad FPU
(4-wide double precision, SIMD)
peak performance ******@55W
Central shared L2 cache: 32 MB
eDRAM
multiversioned cache will support transactional memory, speculative execution.
supports atomic ops
Dual memory controller
16 GB external DDR3 memory
Gb/s
2 * 16 byte-wide interface (+ECC)
Chip-to-working
Router logic integrated into BQC chip.
External IO
PCIe Gen2 interface
System-on-a-Chip design : integrates processors, memory working logic into a single chip