文档介绍：The Stanford Dash
Multiprocessor
Daniel Lenoski, James Laudon, Kourosh Gharachorloo,
Wolf-Dietrich Weber, Anoop Gupta, John Hennessy,
Mark Horowitz, and Monica S. Lam
Stanford University
puter Systems Laboratory at Stanford University is developing a
shared-memory multiprocessor called Dash (an abbreviation for Direc-
tory Architecture for Shared Memory). The fundamental premise behind
the architecture is that it is possible to build a scalable high-performance machine
with a single address space and coherent caches.
The Dash architecture is scalable in that it achieves linear or near-linear
performance growth as the number of processors increases from a few to a few
thousand. This performance results from distributing the memory among process-
ing nodes and using work with scalable bandwidth to connect the nodes. The
architecture allows shared data to be cached, thereby significantly reducing the
latency of memory accesses and yielding higher processor utilization and higher
Directory-based overall performance. A distributed directory-based protocol provides cache co-
cache coherence gives herence promising scalability.
The Dash prototype system is the first operational machine to include a scalable
Dash the ease-of-use cache-coherence mechanism. The prototype incorporates up to 64 high-perfor-
mance RISC microprocessors to yield performance up to billion instructions
of shared-memory per second and 600 million scalar floating point operations per second. The design
architectures while of the prototype has provided deeper insight into the architectural and implemen-
tation challenges that arise in a large-scale machine with a single address space.
maintaining the The prototype will also serve as a platform for studying real applications and
software on a large parallel system.
scalability of This article begins by describing the overall goals for Dash, the major features
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