文档介绍：毕业设计( 论文)
题目基于CPLD的数字频率计
英文题目 Numeral Frequency meter
Base on CPLD
学生姓名曹红
专业电子信息工程
班级 020212
指导老师黄乡生
二零零六年六月
摘要
本论文主要介绍基于CPLD芯片的8位十进制数字频率计。它的基本测量原理是,首先让被测信号与标准信号同时通过一个闸门,然后用计数器对信号脉冲计数,把标准时间内的计数结果用锁存器锁存,最后用显示译码器把锁存的结果用LED数码管显示出来。本文详细叙述了用VHDL语言进行编程,避免了用电路图设计时所引起的毛刺现象,改变了以往数字电路小规模多器件组合的设计方法。整个频率计设计在一块CPLD芯片上,与用其它方法设计的频率计相比,体积更小,性能更可靠。本设计方案要求,根据被测输入信号的频率范围自动切换量程,控制小数点显示位置,并以十进制形式显示。该设计方案通过了Max+plusⅡ软件仿真、硬件调试和软硬件综合测试。
关键词
CPLD ;VHDL;数字频率计
Abstract
This paper introduces eight metric based on the CPLD chip frequency of such precision figures for the importation of 1Hz to 10MHz sine wave measurements using methods such as precision measuring frequency, pulse width and ratio . Its basic measurement principle is, let detected signals and standards at the same time through a gate signal and then use the signal pulse count counter to the standard time of the count results in latch devices latched, with the final show decoder to use led digital latch results show that control. This article describes in detail the use VHDL executable program, avoid using circuit diagram caused by the design of burr phenomenon, a change in the previous small-scale multi-bination digital circuit design methods. In the frequency of a CPLD chip design, and the frequency of pared to other methods of design, will be smaller, more reliable performance. The design of programs, according to statistical input signal frequency range automatic cut over measuring range, control decimal point location, and to show Metrication form. The design of programs adopted Max+plus II software simulation, hardware and software prehensive testing.
Key Words
CPLD;VHDL; Digital frequency counter
目录
绪论 1
第一章 CPLD简介 2
第二章数字频率计的测量原理 4
测频法 4
测周法 6
测频法和测周法的比较 6
第三章频率计的总体设计 8
设计任务和要求 8
模块设计 8
模块分析与设置 8
频率计模块结构框图 9
数字频率计模块设计 11
控制电路模块 11
计数电路模块 12
锁存电路模块 14
译码电路模块 14
软件设计 15
第四章频率计的调试及实现 16
第五章结论 17
致谢 19
参考文献 20
附录 21