文档介绍：上海交通大学
硕士学位论文
基于时钟产生应用的自偏置锁相环的设计
姓名:钱舜
申请学位级别:硕士
专业:电路与系统
指导教师:陈进;汪宁
20060101
上海交通大学硕士学位论文
摘要
锁相环被广泛的应用于高性能数字系统的时钟产生。随着时钟频率的不断
提升,系统对于锁相环的抖动性能越来越敏感。传统的电荷泵锁相环以其易于
集成于数字电路 CMOS 工艺而逐渐成为设计的主流,但是电荷泵锁相环的环路
参数(带宽,相位裕量,抖动峰(Jitter Peaking))对于工艺变化、电源电压、温
度特性以及输出频率的变化非常敏感,这不仅恶化了输出频率的杂散而且变化
的带宽更有可能增加输出的抖动,直接造成系统的不稳定。
本文首先以工程师的视角对于电荷泵锁相环的原理和结构做了详细的分
析,然后基于时钟产生应用提出了采用跨导转换和电流控制振荡器的自偏置锁
相环的一种新结构,使锁相环的带宽与电源电压、工艺偏差以及环境温度和倍
频因子等变化都无关。电路设计采用 IDT 1p3m CMOS 工艺,通过仿真显
示本文提出的锁相环在 0 摄氏度到 120 度的温度范围,各个工艺偏差以及
700MHz 到 1200MHz 的输出频率范围下,带宽变化小于±17% ,大大小于传统
锁相环相同条件下±±60% ~ 100% 的偏差。
关键词锁相环,自偏置锁相环,时钟发生器,抖动,相位噪声,模
拟电路
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上海交通大学硕士学位论文
Abstract
Phase-locked loops (PLLs) are widely used to generate well-timed on-chip
clocks in high-performance digital systems. As the increasing of system frequency, the
system performance is much more sensitive to the jitter of the clock synchronizing the
data flow inside. Traditional Charge Pump PLLs (CP-PLLs) is superior to the other
implementations for patibility of modern digital CMOS process. However, its
loop parameter (etc. bandwidth, phase margin, jitter peaking) suffers for its large
variation and inconsistence with different process corner, temperature, supply voltage
and output frequency, which will lead to an increase of output jitter and spurs even the
improper system operation.
The dissertation first describes the principle of Charge Pump PLL and analyzes
the definition of jitter from the view of an engineer. Then a new architecture for self-
biased PLL is proposed to achieve constant bandwidth independent of process, power
supply voltage, temperature and output frequency, which uses an extra
transconductance stage and current control oscillator. The PLL is designed for IDT
1p3m CMOS process. Simulation results show less than ±17% variation of
bandwidth, which is far superior to traditional design (around ±50% ~ 100% ).
KEY WORDS phase-locked loop, self-biased phase-locked loop, clock
gen