文档介绍：Austrochip 2008 Johannes Kepler Universität Linz
Design and Simulation of a PCI Express based Embedded System
Faraj Nassar1, Jan Haase1, Christoph Grimm1, Herbert Nachtnebel1, Majid Ghameshlu2
1 Institute puter Technology, Vienna University of Technology
2 Siemens IT Solution and Services PSE, Siemens AG Austria
{nassar, haase, grimm, nachtnebel}***@, @
Abstract In the 1990s, the second IO buses generation was
started with different approaches. In 1993 the PCI 33
In this paper, a brief introduction to the theory of PCI MHz bus was released. At that time, a 32-bit version of
Express (PCIe) bus system is given. In addition to that, this bus was enough to deliver a bandwidth of 133
the capabilities of this bus system are demonstrated by Mbytes/s, which met the bandwidth requirements of the
designing and simulating a PCIe based embedded data available IO peripherals. A 64-bit version of this PCI bus
communication system. This system utilizes the Xilinx delivers a bandwidth of 266 Mbytes/s [1]. However, due
Microblaze soft processor core, the Xilinx PCIe core, to the increase in the processor speeds and the bandwidth
and the Philips PX1011A physical layer. A basic, needs of newer IO technologies, the PCI bus frequency
efficient, and simplified On-chip Peripheral Bus (OPB) was increased in 1995 from 33 to 66 MHz, to increas