文档介绍：VERILOG® QUICKSTART
A Practical Guide to Simulation
and Synthesis in Verilog
Third Edition
THE KLUWER INTERNATIONAL SERIES
IN ENGINEERING PUTER SCIENCE
VERILOG® QUICKSTART
A Practical Guide to Simulation
and Synthesis in Verilog
Third Edition
James M. Lee
Intrinsix Corp.
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
eBook ISBN: 0-306-47680-0
Print ISBN: 0-7923-7672-2
©2002 Kluwer Academic Publishers
New York, Boston, Dordrecht, London, Moscow
Print ©2002 Kluwer Academic Publishers
Dordrecht
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TABLE OF CONTENTS
LIST OF FIGURES xiii
LIST OF EXAMPLES xv
LIST OF TABLES xxi
1 INTRODUCTION 1
Framing Verilog Concepts 3
The Design Abstraction Hierarchy 3
Types of Simulation 4
Types of Languages 4
Simulation versus Programming 5
HDL Learning Paradigms 5
Where To Get More Information 7
Reference Manuals 8
8
2 INTRODUCTION TO THE VERILOG LANGUAGE 9
Identifiers 9
Escaped Identifiers 10
White Space 11
Comments 12
Numbers 12
Text Macros 13
Modules 14
Semicolons 14
Value Set 15
Strengths 15
Numbers, Values, and Unknowns 16
vi Verilog Quickstart
3 STRUCTURAL MODELING 19
Primitives 19
Ports 20
Ports in Primitives 20
Ports in Modules 21
Instances 22
Hierarchy 22
Hierarchical Names 24
Connect by Name 26
Top-Level Modules 27
You Are Now Ready to Run Your First Simulations 28
Exercise 1 The Hello Simulation 28
Exercise 2 The 8-Bit Hierarchical Adder 28
4 STARTING PROCEDURAL MODELING 33
Starting Places for Blocks of Procedural Code 34
The initial Keyword 34
The always Keyword 34
Delays 35
begin-end Blocks 36
fork-join Blocks 39
Summar