文档介绍：SystemVerilog for Verification
A Guide to Learning the Testbench Language Features
Second Edition
Chris Spear
SystemVerilog
for Verification
A Guide to Learning the Testbench
Language Features
Second Edition
Chris Spear
Synopsys, Inc.
Marlboro, MA
USA
Library of Congress Control Number: 2008920031
ISBN 978-0-387-76529-7 e-ISBN 978-0-387-76530-3
Printed on acid-free paper.
©2008 Springer Science+Business Media, LLC
All rights reserved. This work may not be translated or copied in whole or in part without the written
permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY
10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in connection
with any form of information storage and retrieval, electronic adaptation, computer software, or by similar or
dissimilar methodology now known or heareafter developed is forbidden. The use in this publication of trade
names, trademarks, service marks and similar terms, even if they are not identified as such, is not to be taken
as an expression of opinion as to whether or not they are subject to proprietary rights.
While the advice and information in this book are believed to be true and accurate at the date of going to
press, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors
or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the
material contained herein.
9 87654321
This book is dedicated to my wonderful wife Laura,
whose patience during this project was invaluable,
and my children, Allie and Tyler, who kept me laughing.
Contents
List of Examples xiii
List of Figures xxv
List of Tables xxvii
Preface xxix
Acknowledgments xxxv
1. VERIFICATION GUIDELINES 1
The Verification Process 2
The Verification Methodology Manual 4
Basic Testbench Functionality 5
Directed Testing 5
Methodology