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Predicting PLL Phase Noise synopsys·
EDN 8r. Jitter with HSPICE RF
Presenter:
Dr. Scott Wedge, .
HSPICE R&D, Senior Staff
Engineer, Synopsys
HSPICE RF
• Steady-state analysis capabilities for RF signals and noise.
Harmonic Balance and Shooting Newton algorithms for predicting the
steady-state behavior of nonlinear analog and digital circuits.
Oscillator and Phase Noise analyses, including jitter measurements.
Envelope and Modulation analysis for RF signals with mixing and noise.
Quick HSPICE~ accurate simulations with over 10,000 active devices.
synopsys'
Predictable ess
PLL Phase Noise & Jitter
Agenda
• PLL Design Challenges
• Overview of PLL Jitter
• System Level PLL Characterization
• PLL Noise Analysis with HSPICE RF
• References/QA
synopsys'
Predictable ess
PLL Design Challenges
• essful PLL design involves more than verification of its
transient behavior - a necessary but not sufficient step.
synopsys'
Predictable ess
PLL Design Challenges
• PLLs can plex mixed-signal control systems.
8 (s)
8 2(5) KoKdF(S)
8 1(5) s+ KoKdF(S)/ N
• Their design is a delicate tradeoff between:
Stability requirements
Loop dynamics (acquisition time).
Phase noise and jitter characteristics .
• Jitter is the limiting factor in many of today's PLL designs I
synopsys'
Predictable ess
PLL Design Challenges
• Presented here is a design/analysis flow that
extracts many of the key characteristics of PLL
behavior.
• The focus is on making accurate predictions for
PLL phase noise and jitter.
• This is plished using the steady-state signal
and noise analysis capabilities of HSPICE RF.
• Also extracted are parameters critical for analyzing
loop dynamics and loop stability characteristics.
synopsys'
Predictable ess
Overview of PLL Jitter
• PLLs take a relatively low-stability oscillator (VeOl and use
a feedback loop to track an