VHDL各种D触发器程序.docx

文档介绍：第一题:普通触发器LIBRARYIEEE;;ENTITYDchuISPORT(CLK,D:INSTD_LOGIC;Q:OUTSTD_LOGIC);END;ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_LOGIC;BEGINPROCESS(CLK,Q1)BEGINIFCLK'EVENTANDCLK='1'THENQ1<=D;ENDIF;ENDPROCESS;Q<=Q1;ENDFFQ;Q1~PRED Q—*>ENACLR第二题:异步清零触发器LIBRARYIEEE;;ENTITYDchuISPORT(CLK,D:INSTD_LOGIC;Q:OUTSTD_LOGIC;ACLK:INSTD_LOGIC);END;ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_LOGIC;BEGINPROCESS(ACLK,CLK,Q1)BEGINIFACLK='1'THENQ1<='0';ELSIFCLK'EVENTANDCLK='1'THENQ1<=D;ENDIF;ENDPROCESS;Q<=Q1;ENDFFQ;Q1CLKI >PKE□>CIRAULK >第三题:同步清零触发器LIBRARYIEEE;;ENTITYDchuISPORT(CLK,D:INSTD_LOGIC;Q:OUTSTD_LOGIC;SCLK:INSTD_LOGIC);END;ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_LOGIC;BEGINPROCESS(SCLK,CLK,Q1)BEGINIFCLK'EVENTANDCLK='1'THENIFSCLK='1'THENQ1<='0:ELSEQ1<=D;ENDIF;ENDIF;ENDPROCESS;Q<=Q1;ENDFFQ;第四题:异步置位apreLIBRARYIEEE;;ENTITYDchuISPORT(CLK :INSTD_LOGIC;D :INSTD_LOGIC;Q :OUTSTD_LOGIC;APRE :INSTD_LOGIC);END;ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_LOGIC;BEGINPROCESS(APRE,CLK,Q1)BEGINIFAPRE='1'THENQ1<='1';ELSIFCLK'EVENTANDCLK='1'THENQ1<=D;ENDIF;ENDPROCESS;Q<=Q1;31口RED>zCLftENDFFQ;AFRE一>DI>CLK匚二>第五题:同步置位spreLIBRARYIEEE;;ENTITYDchuISPORT(CLK:INSTD_LOGIC;D :INSTD_LOGIC;Q :OUTSTD_LOGIC;SPRE:INSTD_LOGIC);END;ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_LOGIC;BEGINPROCESS(SPRE,CLK,Q1)BEGINIFCLK'EVENTANDCLK='1'THENIFSPRE='1'THENQ1<='1';ELSEQ1<=D;ENDIF;ENDIF;ENDPROCESS;Q<=Q1;ENDFFQ;第六题:异步清零,异步置位LIBRARYIEEE;;ENTITYDchuISPORT(CLK:INSTD_LOGIC;ACLR:INSTD_LOGIC;APRE:INSTD_LOGIC;D:INSTD_LOGIC;Q:OUTSTD_LOGIC);END;ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_LOGIC;BEGINPROCESS(APRE,ACLR,CLK,Q1)BEGINIFACLR='1'THENQ1<='0';ELSIFAPRE='1'THENQ1<='1';ELSIFCLK'EVENTANDCLK='1'THENQ1<=D;ENDIF;ENDPROCESS;Q<=Q1;ENDFFQ;第七题:同步使能LIBRARYIEEE;;ENTITYDchuISPORT(CLK :INSTD_LOGIC;D :INSTD_LOGIC;Q :OUTSTD_LOGIC;EN :INSTD_LOGIC);END;ARCHITECTUREFFQOFDchuISSIGNALQ1:STD_LOGIC;BEGINPROCESS(EN,CLK,Q