文档介绍：AdvanceAdvance HDLHDL DesignDesign
TrainingTraining OnOn XilinxXilinx FPGAFPGA
Yu-Tsang/Carven Chang
Associate Researcher, CIC/NSC
******@
February, 2001
/XLNX_HDL Intro-1
Outline I CIC
! FPGA Express Overview
! Xilinx HDL Synthesis Flow
! Architecture
! Introduce to FPGA Design
! HDL Coding
! LAB I
/XLNX_HDL Intro-2
Outline II CIC
! Black Box Instantiation
! Introduce to Efficient Synthesis
! Timing Constraints with Foundation Express
! Simulation with Foundation lists
! Xilinx CORE Generator
! Synopsys FPGA Express & Xilinx Design Manager
! LAB II
/XLNX_HDL Intro-3
FGPA Express
/XLNX_HDL Exp-1
What is FPGA Express? CIC
! plete FPGA logic-synthesis and optimization
tool.
! Provide an integrated text editor
! Analyze HDL(VHDL and Verilog HDL) design source files for
correct syntax using Synopsys industry-standard HDL policy
! accept bination of VHDL, Verilog HDL, and FPGA
netlist files as sources for a single design
! Use architecture-specific algorithms to target Xilinx
device(FPGA and CPLD)
! Optimize logic for speed and area as directed by your
design constraints.
! Extract and display accurate post-synthesis delay
information for timing analysis and debugging
/XLNX_HDL Exp-2
FPGA Express Features CIC
! FPGA Express Device Support
! 3K A, 4K E / L / EX / XL / XV
! Spartan, 5200, 9500
! Virtex, Virtex-E, Virtex-II
! Xilinx Architecture-Specific Algorithms for Best
Optimization
! Verilog (IEEE 1364) and VHDL (IEEE 1076-1987)
Support
! piler II
! Design Ware, Contraint-driven, retiming…
/XLNX_HDL Exp-3
FPGA Express Features ... CIC
! FPGA Express Technology
! Constraint Entry GUI
! Automatic I/O Pad and Global Signal Mapping
! Built-in Timing Analyzer
! Built-in Module Generation (Fast Carry, RLOC)
! Resource Sharing
! Hie