文档介绍：MOCL005-FM MOCL005- June 27, 2008 8:35
COMPUTER
ARCHITECTURE
TECHNIQUES FOR
POWER-EFFICIENCY
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Synthesis Lectures puter
Architecture
Editor
Mark D. Hill, University of Wisconsin, Madison
Synthesis Lectures puter Architecture publishes 50 to 150 page publications on topics
pertaining to the science and art of designing, analyzing, selecting and interconnecting hardware
components to puters that meet functional, performance and cost goals.
Computer Architecture Techniques for Power-Efficiency
Stefanos Kaxiras and Margaret Martonosi
2008
Chip Mutiprocessor Architecture: Techniques to Improve Throughput and Latency
Kunle Olukotun, Lance Hammond, James Laudon
2007
Transactional Memory
James R. Larus, Ravi Rajwar
2007
puting puter Architects
Tzvetan S. Metodi, Frederic T. Chong
2006
MOCL005-FM MOCL005- June 27, 2008 8:35
Copyright © 2008 by Morgan & Claypool
All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in
any form or by any means—electronic, mechanical, photocopy, recording, or any other except for brief quotations
in printed reviews, without the prior permission of the publisher.
Computer Architecture Techniques for Power-Efficiency
Stefanos Kaxiras and Margaret Martonosi
ISBN: 9781598292084 paper
ISBN: 9781598292091 ebook
DOI:
A Publication in the Morgan & Claypool Publishers series
SYNTHESIS LECTURES PUTER ARCHITECTURE #4
Lecture #4
Series Editor: Mark D. Hill, University of Wisconsin, Madison
Library of Congress Cataloging-in-Publication Data
Series ISSN: 1935-3235 print
Series ISSN: 1935-3243 electronic
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MOCL005-FM MOCL005- June 27, 2008 8:35
COMPUTER
ARCHITECTURE
TECHNIQUES FOR
POWER-EFFICIENCY
Stefanos Kaxiras
University of Patras, Greece
Kaxiras@