文档介绍：(2,1 ,7)卷积码Viterbi译码器FPGA实现方案
(
韩
北京
可1，邓中亮1，施乐宁
100876 ; 电子信息工程学院
北京 100083)
摘 要：移动通信系统标准中普遍采用卷积码作为信道编码方案 。本文阐述了目前最常用的卷积码译码算法 一Vit 2
erbi译码算法，然后给岀了(2,1,7)卷积码编码电路 FPGA实现方法。该方法给岀了新的 Viterbi幸运路径算法和高效的状
态度量存储技术，可以充分利用FP GA的优势获得较好的译码结果。利用幸存路径交换寄存器模块 ，能有效减少存储量并
降低功耗。
关键词:Viterbi译码；FPGA;卷积码；寄存器交换；回溯
中图分类号：TN74 文献标识码:B 文章编号：1004 - 373X (2007) 15 - 090 - 03
FPGA Implementation in the Viterbi Decoding Scheme of ( 2 ,1 ,7) Convolutional Code
HAN Ke1 ,DEN G Zhongliang 1 ,SHI Lening 2
(1. School of Electro nic Engin eeri ng ,Beiji ng Uni versity of Posts a nd Telecomm uni cati ons ,Beiji ng ,100876 ,Chi na;
2. School of Electronic and Information Engineering ,Beihang University ,Beijing ,100083 ,China)
Abstract :Convolutional code are universally used in the norm of mobile communication system. This paper first analyzes the principle of Viterbi algorithm ,which is the optimal decoding scheme for convolutional codes. Then the paper also presents the FP GA implementation in the Viterbi decoding scheme of (2 ,1 ,7) convolutional code. The method gives the new branch weight algorithm and uniform state weight memories ,so it can take advantage of the FP GA. By the design of survival path ex2 change register module ,the power consumption and the RAM size are needed for saving metrics are decreased.
Keywords :Viterbi decoding ; FP GA ;convolutional co