文档介绍：Quartus®IISoftwareDesignSeries:TimingAnalysis-Timinganalysisbasics*pleteunderstandingoftiminganalysis*Howdoestimingverificationwork?Everydevicepathindesignmustbeanalyzedwithrespecttotimingspecifications/requirementsCatchtiming-relatederrorsfasterandeasierthangate-levelsimulation&boardtestingDesignermustentertimingrequirements&exceptionsUsedtoguidefitterduringplacement&pareagainstactualresultsbinationaldelaysCLR*&holdtimesData&clockarrivaltimeDatarequiredtimeSetup&holdslackanalysisI/OanalysisRecovery&removalTimingmodels*Path&AnalysisTypesThreetypesofPaths:ClockPathsDataPathAsynchronousPaths*ClockPathsAsyncPathDataPathAsyncPathDQCLRPREDQCLRPRETwotypesofAnalysis:Synchronous –clock&datapathsAsynchronous* –clock&asyncpaths*Asynchronousreferstosignalsfeedingtheasynchronouscontrolportsoftheregisters*Launch&LatchEdgesCLKLaunchEdgeLatchEdgeDataValidDATALaunchEdge: theedgewhich“launches”thedatafromsourceregisterLatchEdge: theedgewhich“latches”thedataatdestinationregister(withrespecttothelaunchedge,selectedbytiminganalyzer;typically1cycle)*Setup&HoldSetup: Theminimumtimedatasignalmustbestable BEFOREclockedgeHold: Theminimumtimedatasignalmustbestable AFTERclockedgeDQCLRPRECLKThValidDATATsuCLKDATATogether,thesetuptimeandholdtimeformaDataRequiredWindow,thetimearoundaclockedgeinwhichdatamustbestable.*DataArrivalTimeDataArrivalTime=launchedge+Tclk1+Tco+’*ClockArrivalTimeClockArrivalTime=latchedge+’*DataRequiredTime-SetupDataRequiredTime=ClockArrivalTime-Tsu-