文档介绍：华中科技大学
硕士学位论文
一种用于12位40 MHz流水线ADC的采样保持电路的研究与设计
姓名:王文平
申请学位级别:硕士
专业:微电子与固体电子学
指导教师:应建华
20080501
摘要
目前流水线型ADC因其较高的速度、高精度和较低的功耗被广泛应用于各类便携
式视频设备及无线通信设备中。而采样保持做为流水线型ADC的最前端部分,其速度、
精度和功耗将决定着整体ADC的性能。因而研究设计好高速高精度采样保持电路对于
设计流水线型ADC有着至关重要的作用。
本文首先介绍了采样保持电路的工作原理、性能指标和误差来源,然后分别针对
采样保持电路的各个关键模块做了详细的研究和分析。
基于对采样保持的深入研究和探讨,最终我们的采样保持电路的设计方案如下:
1、整体采样保持结构采用的是全差分的电容翻转式结构,这是因为全差分结构可以
很好的抑制来自衬底的共模噪声,降低各种非线性因素引入的失真,其缺点是版图更
复杂,且需要共模反馈电路来稳定输出共模,而电容翻转式结构有较小的噪声和功耗,
并且电容翻转型结构没有电容匹配的问题,不会产生由于电容的不匹配而导致的增益
误差;2、输入采样开关采用的是带哑元补偿管的栅压自举开关,减小了采样开关的
导通电阻以及由于MOS开关导通电阻的非线性导致的采样非线性失真;3、做为采样保
持电路核心的运算放大器,我们采用的是带增益提高辅助运放的折叠式共源共栅运算
放大器,满足了对运放高增益、高带宽以及较小的功耗的要求。
最后, μm CMOS工艺库,在Cadence环境下对整体电路
和分块电路进行了仿真和分析。该电路在3V的电源电压下实现了40 MHz采样频率,采
样精度可达13 位,完全适用于12 位40 MHz流水线型ADC的前端采样部分。

关键词:ADC; 采样保持电路; 栅压自举开关; 增益提高运算放大器

I
ABSTRACT
In recent years, Pipeline ADC is widely used in the portable video device and wireless
mobile, due to its high speed high resolution and low power consumption. Sample/Hold
Circuit (S/H) is the most forward part of Pipeline ADC, and its speed resolution and power
consumption will mostly determine the performance of the whole ADC. So to study and
design a Sample/Hold Circuit with high speed high resolution is very crucial to the Pipeline
ADC.
Firstly, we introduce the Sample/Hold Circuit, analyzing its working principle
performance index and the source of error. And then, we analyze the important part of the
S/H in detail.
Based on the studies, the S/H we designed uses the fully differential flip-around
structure, the fully differential topology can lower mon mode noise from the bulk,
and also can lower the distortion caused by many non-linearity factor, but it makes the
layout plex and mon mode feedback circuit. The flip-around structure
has lower noise and power consumption, and hasn’t the gain error caused by the matching
problem of the capacitances. Bootstrapped switch with dummy device is used to