文档介绍：If you survey hardware design groups, you will learn that between
60 and 80 percent of their effort is now dedicated to verification.
Unlike synthesizeable coding, there is no particular coding style
required for verification. The freedom of using any features of the
languages has produced a wide array of techniques and approaches
to verification. The absence of constraints and lack of available
expertise and references in verification has resulted in ad hoc
approaches. The consequences of an informal verification process
can range from a non-functional design requiring several re-spins,
through a design with only a subset of the intended functionality, to
a delayed product shipment.
WHY THIS BOOK IS IMPORTANT
Take a survey of the books about Verilog or VHDL currently avail-
able. You will notice that the majority of the pages are devoted to
explaining the details of the languages. In addition, several chapters
are focused on the synthesizeable coding style - or RTL - replete
with examples. Some books are even devoted entirely to the subject
of RTL coding.
When verification is addressed, only one or two chapters are dedi-
cated to the topic. And often, the primary focus is to introduce more
language constructs. Verification is often presented in a very rudi-
mentary fashion, using simple techniques that e tedious in
large-scale, real-life designs.
Writing Testbenches: Functional Verification of HDL Models xvii
Preface
Basic language textbooks appeared early in the life of hardware
description languages. They continue to appear as the presentation
styles are refined to facilitate their understanding or as they are
tuned to a particular audience. But the benefits of additional lan-
guage textbooks is quickly diminishing.
Since the introduction of hardware description languages and logic
synthesis technology in the mid 80's, a lot of expertise on coding
styles and synthesis meth