文档介绍：WRITING TESTBENCHES
Functional Verification of HDL Models
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WRITING TESTBENCHES
Functional Verification of HDL Models
Janick Bergeron
Qualis Design Corporation
KLUWER ACADEMIC PUBLISHERS
NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
eBook ISBN: 0-306-47687-8
Print ISBN: 0-7923-7766-4
©2002 Kluwer Academic Publishers
New York, Boston, Dordrecht, London, Moscow
Print ©2000 Kluwer Academic Publishers
Dordrecht
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TABLE OF CONTENTS
About the Cover xiii
Foreword xv
Preface xvii
Why This Book Is Important xvii
What This Book Is About xviii
What Prior Knowledge You Should Have xix
Reading Paths xx
VHDL versus Verilog xx
For More Information xxii
Acknowledgements xxii
CHAPTER 1 What is Verification? 1
What is a Testbench? 1
The Importance of Verification 2
Reconvergence Model 4
The Human Factor 5
Automation 6
Poka-Yoka 6
Writing Testbenches: Functional Verification of HDL Models v
Table of Content
Redundancy 6
What Is Being Verified? 7
Formal Verification 7
Equivalence Checking 8
Model Checking 9
Functional Verification 10
Testbench Generation 11
Functional Verification Approaches 11
Black-Box Verification 12
White-Box Verification 13
Grey-Box Verification 13
Testing Versus Verification 13
Scan-Based Testing 14
Design for Verification 16
Verification and Design Reuse 16
Reuse Is About Trust 16
Verification for Reuse 17
The Cost of Verification 17
Summary 19
CHAPTER 2 Verification Tools 21
Linting Tools 22
The Limitations of Linting Tools 23
Linting Verilog Source Code 25
Linting VHDL Source Code 26
Code Reviews 28
Simulators 28