数字系统设计复习.doc

文档介绍：一请用VHDL语言设计一个矩阵式键盘译码电路,输入端口为(clk,ky[1..0],kx[2..0]),输出端口为(yout[2..0],只要求将键值输出即可,不需要输出标志位,其中功能键和数字键统一编码,编码表如表1所示,键盘连线如图1所示。
表1
按键
编码
按键
编码
按键
编码
1
001
2
010
3
011
4
100
5
101
6
110
LIBRARY IEEE;
USE ;
USE ;
USE ;
ENTITY ZZJPYM IS
PORT (CLK: INSTD_LOGIC ;
Y: IN STD_LOGIC_VECTOR (1 DOWNTO 0) ;
x: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
yout: OUT STD_LOGIC_VECTOR(2 DOWNTO 0) ;
END ENTITY ZZJPYM ;
ARCHITECTURE ART OF ZZJPYM IS
SIGNAL N: STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
PROCESS(CLK)
BEGIN
Z <=y & x;
IF CLK'EVENT AND CLK = '1' THEN
CASE Z IS
WHEN "10011" => N <= "0001" ; --1
WHEN "10101" => N <= "0010" ; --2
WHEN "10110" => N <= "0011" ; --3
WHEN "01011" => N <= "0100" ; --4
WHEN "01101" => N <= "0101" ; --5
WHEN "01110" => N <= "0110" ; --6
WHEN OTHERS => N <= "1111" ;
END CASE ;
END IF ;
yout<=N;
END ARCHITECTURE ART;
二用VHDL设计一个显示控制电路,将4个共阳数码管上显示“4321”数据,其外部电路的接线示意图如图2所示。该控制器输入端口为(clk),[3..0],seg[7..0])。
LIBRARY IEEE;
USE ;
USE ;
ENTITY DISPLAY IS
PORT(CLK:IN STD_LOGIC;-
COM:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
SEG: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END ENTITY DISPLAY;
ARCHITECTURE ART OF DISPLAY IS
T:STD_LOGIC_VECTOR(1 DOWNTO 0);
PROCESS(CLK)
BEGIN
IF CLK'EVENT AND CLK