文档介绍：: .
VHDL .............................................................2-3
Package ..............................................................................2-3
Entity .................................................................................2-4
Architecture.........................................................................2-5
Configuration.......................................................................2-5
Statements ..............................................................................2-6
Declaration Statements.........................................................2-6
Concurrent and Sequential Statements ...................................2-6
Data Objects.............................................................................2-8
Variables.............................................................................2-8
Constants............................................................................2-9
Signals ...............................................................................2-9
Data Types............................................................................. 2-11
Numeric Types................................................................... 2-12
Other Types....................................................................... 2-13
Enumerated Types.............................................................. 2-13
The Std_ulogic and Std_logic Data Types .............................. 2-14
User Defined Types and Subtypes ........................................